The present disclosure relates to the capacitance extraction and more specifically, to a method for improving capacitance extraction performance by approximating the effect of distant shapes.
Capacitance extraction is important to create reliable circuit designs in order to emulate actual digital and analog circuit responses. The data that is obtained from the extraction includes delay information, simulation data, and signal integrity data of the metal wires. When performing a typical extraction for a target wire all of the metal pieces within a three-dimensional region around the target wire are included in the computation. As the number of global interconnects increase in the design, the number of nets and shapes making up the nets will increase the number of design elements to be analyzed in the extraction. In addition, the variation of the shapes and interconnects adds complexity to the extraction analysis, which becomes very computer-intensive to process taking many hours to a few days to complete depending on the available resources and the desired accuracy. Parasitic capacitance must be considered when designing integrated circuits having multiple wiring layers to ensure the reliability and performance of the device.